232 search results - page 1 / 47 » Generalised Resource Model for Parallel Instruction Scheduli... |
PARELEC
2006
IEEE
13 years 11 months ago
2006
IEEE
IEEEPACT
2003
IEEE
13 years 10 months ago
2003
IEEE
Effective modeling and management of hardware resources have always been critical toward generating highly efficient code in static compilers. With Just-In-Time compilation and dy...
PLDI
1995
ACM
13 years 8 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
ASPLOS
1998
ACM
13 years 9 months ago
1998
ACM
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
ICS
1999
Tsinghua U.
13 years 9 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...