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PTS
2008
80views Hardware» more  PTS 2008»
13 years 6 months ago
Generating Checking Sequences for Partial Reduced Finite State Machines
The problem of generating checking sequences for FSMs with distinguishing sequence has been attracting interest of researchers for several decades. In this paper, a solution is pro...
Adenilso da Silva Simão, Alexandre Petrenko
ASE
2006
123views more  ASE 2006»
13 years 4 months ago
Separating sequence overlap for automated test sequence generation
Finite state machines have been used to model a number of classes of system and there has thus been much interest in the automatic generation of test sequences from finite state m...
Robert M. Hierons
ASE
2010
126views more  ASE 2010»
13 years 4 months ago
Generating a checking sequence with a minimum number of reset transitions
Given a finite state machine M, a checking sequence is an input sequence that is guaranteed to lead to a failure if the implementation under test is faulty and has no more states t...
Robert M. Hierons, Hasan Ural
ISCIS
2009
Springer
13 years 11 months ago
Using a SAT solver to generate checking sequences
—Methods for software testing based on Finite State Machines (FSMs) have been researched since the early 60’s. Many of these methods are about generating a checking sequence fr...
Guy-Vincent Jourdan, Hasan Ural, Hüsnü Y...