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» Generating functions for the area below some lattice paths
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ISSS
1999
IEEE
157views Hardware» more  ISSS 1999»
13 years 9 months ago
Bit-Width Selection for Data-Path Implementations
Specifications of data computations may not necessarily describe the ranges of the intermediate results that can be generated. However, such information is critical to determine t...
Carlos Carreras, Juan A. López, Octavio Nie...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 2 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson