3 search results - page 1 / 1 » Generation and Analysis of Hard to Round Cases for Binary Fl... |
ARITH
2001
IEEE
13 years 8 months ago
2001
IEEE
ARITH
2009
IEEE
13 years 8 months ago
2009
IEEE
This paper deals with the design and implementation of low latency software for binary floating-point division with correct rounding to nearest. The approach we present here targe...
ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...