44 search results - page 9 / 9 » Generation of Executable Representation for Processor Simula... |
ISCA
2006
IEEE
13 years 11 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
DEDS
2000
13 years 4 months ago
2000
In this paper, we present the integration of controller synthesis techniques in the SIGNAL environment through the description of a tool dedicated to the incremental construction o...
ECMDAFA
2010
Springer
13 years 8 months ago
2010
Springer
Dynamic UML models like sequence diagrams (SD) lack sufficient formal semantics, making it difficult to build automated tools for their analysis, simulation and validation. A commo...
JSA
2000
13 years 4 months ago
2000
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...