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» Glitch-free design for multi-threshold CMOS NCL circuits
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GLVLSI
2009
IEEE
201views VLSI» more  GLVLSI 2009»
13 years 7 months ago
Glitch-free design for multi-threshold CMOS NCL circuits
In this paper, a novel design is proposed for eliminating glitches and signal bounces during wake-up events that result from incorporating multi-threshold CMOS (MTCMOS) into async...
Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia D...
DAC
1997
ACM
13 years 8 months ago
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
James Kao, Anantha Chandrakasan, Dimitri Antoniadi...
DATE
2005
IEEE
140views Hardware» more  DATE 2005»
13 years 10 months ago
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switc...
Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami,...
ISLPED
1998
ACM
155views Hardware» more  ISLPED 1998»
13 years 8 months ago
Low threshold CMOS circuits with low standby current
Multi-Voltage CMOS MVCMOS is a design methodology for very low power supply voltages that uses low-threshold transistors in series with the supply rails. The control voltages on...
Mircea R. Stan
DAC
2006
ACM
14 years 5 months ago
Charge recycling in MTCMOS circuits: concept and analysis
Designing an energy efficient power gating structure is an important and challenging task in Multi-Threshold CMOS (MTCMOS) circuit design. In order to achieve a very low power des...
Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram