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ICCD
2004
IEEE
120views Hardware» more  ICCD 2004»
12 years 6 months ago
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs
This paper describes XTalkDelay, an industrial-strength methodology and tool for measuring the impact of crosstalk on delays of paths in a design. The main cornerstone of XTalkDel...
Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwin...
ICCAD
2000
IEEE
153views Hardware» more  ICCAD 2000»
12 years 1 months ago
Slope Propagation in Static Timing Analysis
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
David Blaauw, Vladimir Zolotov, Savithri Sundaresw...
CODES
2003
IEEE
12 years 3 months ago
Synthesis of real-time embedded software with local and global deadlines
Current methods cannot synthesize real-time embedded software applications when the global deadline of a task is shorter than the total of all local deadlines along a critical pat...
Pao-Ann Hsiung, Cheng-Yi Lin
TCAD
2008
114views more  TCAD 2008»
11 years 9 months ago
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
David A. Papa, Tao Luo, Michael D. Moffitt, Chin-N...
DATE
2005
IEEE
139views Hardware» more  DATE 2005»
12 years 3 months ago
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model
— State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated due to global source of variations and path r...
Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chun...
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