10 search results - page 1 / 2 » Global interconnect sizing and spacing with consideration of... |
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of couplin...
ASPDAC
1998
ACM
13 years 8 months ago
1998
ACM
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
ICCAD
1993
IEEE
13 years 8 months ago
1993
IEEE
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
With the exponential reduction in the scaling of feature size, inter-wire coupling capacitance becomes the dominant part of load capacitance. Two problems are introduced by coupli...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating ...