3 search results - page 1 / 1 » Hardened by Design Techniques for Implementing Multiple-Bit ... |
ISCAS
2007
IEEE
13 years 10 months ago
2007
IEEE
— We present a novel MBU-tolerant design, which utilizes layout-based interleaving and multiple-node disruption tolerant memory latches. This approach protects against grazing in...
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
EDCC
2006
Springer
13 years 8 months ago
2006
Springer
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...