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» Hardware Accelerated Power Estimation
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ASPDAC
2007
ACM
131views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...
Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen
AAAI
2004
13 years 6 months ago
Visual Odometry Using Commodity Optical Flow
A wide variety of techniques for visual navigation using robot-mounted cameras have been described over the past several decades, yet adoption of optical flow navigation technique...
Jason Campbell, Rahul Sukthankar, Illah R. Nourbak...
SIGMETRICS
2008
ACM
101views Hardware» more  SIGMETRICS 2008»
13 years 5 months ago
How to parameterize models with bursty workloads
Although recent advances in theory indicate that burstiness in the service time process can be handled effectively by queueing models (e.g., MAP queueing networks [2]), there is a...
Giuliano Casale, Ningfang Mi, Ludmila Cherkasova, ...
ACSD
2010
IEEE
255views Hardware» more  ACSD 2010»
13 years 3 months ago
From POOSL to UPPAAL: Transformation and Quantitative Analysis
POOSL (Parallel Object-Oriented Specification Language) is a powerful general purpose system-level modeling language. In research on design space exploration of motion control syst...
Jiansheng Xing, Bart D. Theelen, Rom Langerak, Jac...
DAC
2002
ACM
14 years 6 months ago
Scheduler-based DRAM energy management
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
Victor Delaluz, Anand Sivasubramaniam, Mahmut T. K...