12 search results - page 1 / 3 » Hardware Implementation of a Montgomery Modular Multiplier i... |
IPPS
2003
IEEE
13 years 9 months ago
2003
IEEE
This paper describes a hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of Public Key Cryptogra...
CHES
2001
Springer
13 years 9 months ago
2001
Springer
This paper describes an algorithm and architecture based on an extension of a scalable radix-2 architecture proposed in a previous work. The algorithm is proven to be correct and t...
IPPS
1999
IEEE
13 years 8 months ago
1999
IEEE
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— High secure cryptographic systems require large bit-length encryption keys which presents a challenge to their efficient hardware implementation especially in embedded devices...
TC
2010
12 years 11 months ago
2010
This paper proposes two improved interleaved modular multiplication algorithms based on Barrett and Montgomery modular reduction. The algorithms are simple and especially suitable ...