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2000
ACM
13 years 8 months ago
Hardware Prediction for Data Coherency of Scientific Codes on DSM
This paper proposes a hardware mechanism for reducing coherency overhead occurring in scientific computations within DSM systems. A first phase aims at detecting, in the address s...
Jean-Thomas Acquaviva, William Jalby
HPCA
1998
IEEE
13 years 9 months ago
Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
Run-time parallelization is often the only way to execute the code in parallel when data dependence information is incomplete at compile time. This situation is common in many imp...
Ye Zhang, Lawrence Rauchwerger, Josep Torrellas
DSD
2009
IEEE
136views Hardware» more  DSD 2009»
13 years 8 months ago
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
Pierfrancesco Foglia, Francesco Panicucci, Cosimo ...
ISPASS
2005
IEEE
13 years 10 months ago
Reaping the Benefit of Temporal Silence to Improve Communication Performance
Communication misses--those serviced by dirty data in remote caches--are a pressing performance limiter in shared-memory multiprocessors. Recent research has indicated that tempor...
Kevin M. Lepak, Mikko H. Lipasti
HPDC
2008
IEEE
13 years 11 months ago
StoreGPU: exploiting graphics processing units to accelerate distributed storage systems
Today Graphics Processing Units (GPUs) are a largely underexploited resource on existing desktops and a possible costeffective enhancement to high-performance systems. To date, mo...
Samer Al-Kiswany, Abdullah Gharaibeh, Elizeu Santo...