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» Hardware Reuse at the Behavioral Level
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ICCS
2004
Springer
13 years 11 months ago
Platform-Independent Cache Optimization by Pinpointing Low-Locality Reuse
Abstract. For many applications, cache misses are the primary performance bottleneck. Even though much research has been performed on automatically optimizing cache behavior at the...
Kristof Beyls, Erik H. D'Hollander
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 10 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
MICRO
2007
IEEE
120views Hardware» more  MICRO 2007»
13 years 12 months ago
Scavenger: A New Last Level Cache Architecture with Global Block Priority
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of inte...
Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Maina...
ISORC
2002
IEEE
13 years 10 months ago
Packaging Quality of Service Control Behaviors for Reuse
Two limitations of the current implementations of adaptive QoS behaviors are complexity associated with inserting them into common application contexts and lack of reusability acr...
Richard E. Schantz, Joseph P. Loyall, Michael Atig...
ANSS
2006
IEEE
13 years 11 months ago
Performance Enhancement by Eliminating Redundant Function Execution
Programs often call the same function with the same arguments, yielding the same results. We call this phenomenon, “function reuse”. Previously, we have shown such a behavior ...
Peng Chen, Krishna M. Kavi, Robert Akl