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IESS
2007
Springer
124views Hardware» more  IESS 2007»
13 years 10 months ago
Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning
: Hardware/software partitioning moves software kernels from a microprocessor to custom hardware accelerators. We consider advanced implementation options for accelerators, greatly...
Scott Sirowy, Frank Vahid
ISCAS
1999
IEEE
95views Hardware» more  ISCAS 1999»
13 years 8 months ago
Evaluating iterative improvement heuristics for bigraph crossing minimization
The bigraph crossing problem, embedding the two node sets of a bipartite graph G = V0;V1;E along two parallel lines so that edge crossings are minimized, has application to placeme...
Matthias F. M. Stallmann, Franc Brglez, Debabrata ...
ASPDAC
1999
ACM
113views Hardware» more  ASPDAC 1999»
13 years 8 months ago
An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
C. K. Eem, J. W. Chong
CODES
2005
IEEE
13 years 10 months ago
Iterational retiming: maximize iteration-level parallelism for nested loops
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean ...
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
13 years 9 months ago
Improving Placement under the Constant Delay Model
In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently compute...
Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Luka...