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» Hardware Speedups in Long Integer Multiplication
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IPPS
2009
IEEE
14 years 13 days ago
Exploring the multiple-GPU design space
Graphics Processing Units (GPUs) have been growing in popularity due to their impressive processing capabilities, and with general purpose programming languages such as NVIDIA’s...
Dana Schaa, David R. Kaeli
ISLPED
2003
ACM
96views Hardware» more  ISLPED 2003»
13 years 11 months ago
Effective graph theoretic techniques for the generalized low power binding problem
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...
Azadeh Davoodi, Ankur Srivastava
MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
13 years 10 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
IPPS
1999
IEEE
13 years 10 months ago
FPGA Implementation of Modular Exponentiation
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
Alexander Tiountchik, Elena Trichina
FPL
2010
Springer
180views Hardware» more  FPL 2010»
13 years 3 months ago
A Karatsuba-Based Montgomery Multiplier
Abstract--Modular multiplication of long integers is an important building block for cryptographic algorithms. Although several FPGA accelerators have been proposed for large modul...
Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip L...