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ICASSP
2011
IEEE
12 years 8 months ago
Hardware architectures for successive cancellation decoding of polar codes
The recently-discovered polar codes are widely seen as a major breakthrough in coding theory. These codes achieve the capacity of many important channels under successive cancella...
Camille Leroux, Ido Tal, Alexander Vardy, Warren J...
GLOBECOM
2008
IEEE
13 years 11 months ago
Near-Capacity Three-Stage Downlink Iteratively Decoded Generalized Layered Space-Time Coding with Low Complexity
Abstract— This paper presents a low complexity iteratively detected space-time transmission architecture based on Generalized Layered Space-Time (GLST) codes and IRregular Convol...
Lingkun Kong, Soon Xin Ng, Lajos Hanzo
GLOBECOM
2008
IEEE
13 years 11 months ago
Rateless Codes for MIMO Channels
— Two rateless code constructions are developed for efficient communication over multi-input multi-output (MIMO) Gaussian channels. The key ingredients in both architectures are...
Maryam Modir Shanechi, Uri Erez, Gregory W. Wornel...
CASES
2004
ACM
13 years 10 months ago
Hardware assisted control flow obfuscation for embedded processors
+ With more applications being deployed on embedded platforms, software protection becomes increasingly important. This problem is crucial on embedded systems like financial transa...
Xiaotong Zhuang, Tao Zhang, Hsien-Hsin S. Lee, San...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
13 years 9 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita