13 search results - page 1 / 3 » Hardware software co-design architecture for thermal managem... |
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
TCAD
2008
13 years 4 months ago
2008
Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower de...
GLVLSI
2007
IEEE
13 years 10 months ago
2007
IEEE
Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power densi...
DATE
2008
IEEE
13 years 10 months ago
2008
IEEE
As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in Multiprocessor Systems on Chip (MPSoCs) can serious...
CODES
2007
IEEE
13 years 10 months ago
2007
IEEE
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...