3 search results - page 1 / 1 » Hardware synthesis from guarded atomic actions with performa... |
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
LCTRTS
2010
Springer
13 years 2 months ago
2010
Springer
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...