17 search results - page 3 / 4 » Hiding Memory Latency using Dynamic Scheduling in Shared-Mem... |
ISCA
1997
IEEE
13 years 10 months ago
1997
IEEE
Current microprocessors aggressively exploit instructionlevel parallelism (ILP) through techniques such as multiple issue, dynamic scheduling, and non-blocking reads. Recent work ...
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
CASES
2004
ACM
13 years 11 months ago
2004
ACM
A coarse-grain multithreaded processor can effectively hide long memory latencies by quickly switching to an alternate task when the active task issues a memory request, improving...
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
EUROPAR
2008
Springer
13 years 7 months ago
2008
Springer
Over the last decade, Message Passing Interface (MPI) has become a very successful parallel programming environment for distributed memory architectures such as clusters. However, ...