12 search results - page 2 / 3 » Hiding Synchronization Delays in a GALS Processor Microarchi... |
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
HIPEAC
2007
Springer
13 years 11 months ago
2007
Springer
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
ASPDAC
2004
ACM
13 years 9 months ago
2004
ACM
- Globally-Asynchronous, Locally-Synchronous (GALS) design style has started to gain interest recently as a possible solution to the increased design complexity, power and thermal ...
HPCA
1999
IEEE
13 years 9 months ago
1999
IEEE
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
NOCS
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...