38 search results - page 7 / 8 » Hierarchical Instruction Register Organization |
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This s...
ICML
1999
IEEE
13 years 10 months ago
1999
IEEE
Developing automated agents that intelligently perform complex real world tasks is time consuming and expensive. The most expensive part of developing these intelligent task perfo...
ASAP
2007
IEEE
14 years 4 days ago
2007
IEEE
Existing SIMD extensions cannot efficiently vectorize the histogram function due to memory collisions. We propose two techniques to avoid this problem. In the first, a hierarchi...
CASES
2007
ACM
13 years 9 months ago
2007
ACM
The last decade has witnessed the emergence of the Application Specific Instruction-set Processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...