22 search results - page 1 / 5 » Hierarchical Interconnects for On-Chip Clustering |
IPPS
2002
IEEE
13 years 9 months ago
2002
IEEE
In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of cl...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
ICPP
2008
IEEE
13 years 10 months ago
2008
IEEE
In this paper, we explore the use of hierarchically structured multiprocessor tasks (M-tasks) for programming multi-core cluster systems. These systems often have hierarchically s...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
In this paper, we utilize Rent’s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design c...
HPCA
2009
IEEE
14 years 4 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...