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» Hierarchical Optimization of Asynchronous Circuits
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DAC
1995
ACM
10 years 4 months ago
Hierarchical Optimization of Asynchronous Circuits
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
Bill Lin, Gjalt G. de Jong, Tilman Kolks
ASYNC
2007
IEEE
132views Hardware» more  ASYNC 2007»
10 years 7 months ago
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
DATE
2004
IEEE
139views Hardware» more  DATE 2004»
10 years 5 months ago
From Synchronous to Asynchronous: An Automatic Approach
This paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case stu...
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno...
ICCAD
2008
IEEE
150views Hardware» more  ICCAD 2008»
10 years 10 months ago
Performance estimation and slack matching for pipelined asynchronous architectures with choice
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
Gennette Gill, Vishal Gupta, Montek Singh
VLSI
2005
Springer
10 years 6 months ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...
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