64 search results - page 1 / 13 » Hierarchical Optimization of Asynchronous Circuits |
DAC
1995
ACM
13 years 8 months ago
1995
ACM
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
ASYNC
2007
IEEE
13 years 10 months ago
2007
IEEE
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case stu...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
VLSI
2005
Springer
13 years 10 months ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...