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» Hierarchical Optimization of Asynchronous Circuits
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ICCAD
2003
IEEE
115views Hardware» more  ICCAD 2003»
14 years 1 months ago
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
ICCAD
1998
IEEE
83views Hardware» more  ICCAD 1998»
13 years 7 months ago
Lazy transition systems: application to timing optimization of asynchronous circuits
This paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzT...
Jordi Cortadella, Michael Kishinevsky, Alex Kondra...
DAC
1998
ACM
13 years 8 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
ASYNC
1998
IEEE
84views Hardware» more  ASYNC 1998»
13 years 8 months ago
Average-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits
We describe an automated method (3D-map) for determining near-optimal decomposed generalized C-element (gC) implementations of extended burst-mode asynchronous controllers. Averag...
Kevin W. James, Kenneth Y. Yun