15 search results - page 2 / 3 » Hierarchically tiled arrays for parallelism and locality |
PDP
2009
IEEE
14 years 1 days ago
2009
IEEE
—Multicore machines are becoming common. There are many languages, language extensions and libraries devoted to improve the programmability and performance of these machines. In ...
ERSA
2009
13 years 3 months ago
2009
For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigur...
IEEEPACT
2009
IEEE
13 years 12 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
PARELEC
2006
IEEE
13 years 11 months ago
2006
IEEE
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
EUROPAR
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. Definitions for the uniform representation of d-dimensional matrices serially in Morton-order (or Z-order) support both their use with cartesian indices, and their divide...