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ISCA
2005
IEEE
91views Hardware» more  ISCA 2005»
13 years 10 months ago
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation
Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Che...
CF
2007
ACM
13 years 8 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee