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» High Level Modeling and Validation Methodologies for Embedde...
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ETS
2007
IEEE
91views Hardware» more  ETS 2007»
13 years 11 months ago
PPM Reduction on Embedded Memories in System on Chip
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests a...
Said Hamdioui, Zaid Al-Ars, Javier Jiménez,...
ACSD
2004
IEEE
124views Hardware» more  ACSD 2004»
13 years 9 months ago
A Behavioral Type Inference System for Compositional System-on-Chip Design
The design productivity gap has been recognized by the semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc s...
Jean-Pierre Talpin, David Berner, Sandeep K. Shukl...
ICSE
2003
IEEE-ACM
14 years 5 months ago
Pattern Oriented Software Development: Moving Seamlessly from Requirements to Architecture
Requirements Engineering (RE) deals with the early phases of software engineering namely requirement elicitation, modeling, specification and validation. Architecture of a softwar...
M. S. Rajasree, P. Jithendra Kumar Reddy, D. Janak...
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
13 years 11 months ago
Heterogeneous behavioral hierarchy for system level designs
Enhancing productivity for designing complex embedded systems requires system level design methodology and language support for capturing complex design in high level models. For ...
Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Ber...
RTSS
2007
IEEE
13 years 11 months ago
ANDES: An ANalysis-Based DEsign Tool for Wireless Sensor Networks
— We have developed an analysis-based design tool, ANDES, for modeling a wireless sensor network system and analyzing its performance before deployment. ANDES enables designers t...
Vibha Prasad, Ting Yan, Praveen Jayachandran, Zeng...