205 search results - page 2 / 41 » High Performance Array Processor for Video Decoding |
IPPS
2002
IEEE
13 years 9 months ago
2002
IEEE
The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging...
CSREAESA
2003
13 years 6 months ago
2003
This paper presents a comparison of power-aware video decoding techniques that utilize Dynamic Voltage Scaling (DVS) capability. Three techniques were simulated and compared in te...
ARCS
2006
Springer
13 years 8 months ago
2006
Springer
: This paper presents the study of modifying a legacy single-issue DSP processor to provide real-time processing capacity for emerging multimedia applications. The latest video com...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) decoding algorithm is gaining increased attention in communication standards and literatur...
IPPS
2008
IEEE
13 years 11 months ago
2008
IEEE
The Sony-Toshiba-IBM Cell Broadband Engine is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD coprocessing units (SPEs) ...