154 search results - page 1 / 31 » High level cache simulation for heterogeneous multiprocessor... |
DAC
2004
ACM
14 years 5 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
DSD
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
APCSAC
2001
IEEE
13 years 8 months ago
2001
IEEE
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
Emerging single-chip heterogeneous multiprocessors feature hundreds of design elements contending for shared resources, making it difficult to isolate performance impacts of indiv...
EUROPAR
1997
Springer
13 years 8 months ago
1997
Springer
The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that...