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ANCS
2009
ACM
13 years 2 months ago
High throughput architecture for packet classification using FPGA
Tao Zhang, Yonggang Wang, Lijun Zhang, Yang Yang
ANCS
2008
ACM
13 years 6 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
DATE
2010
IEEE
190views Hardware» more  DATE 2010»
13 years 9 months ago
Ultra-high throughput string matching for Deep Packet Inspection
Deep Packet Inspection (DPI) involves searching a packet's header and payload against thousands of rules to detect possible attacks. The increase in Internet usage and growing...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
IPPS
2010
IEEE
13 years 2 months ago
Scalable multi-pipeline architecture for high performance multi-pattern string matching
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
Weirong Jiang, Yi-Hua Edward Yang, Viktor K. Prasa...
FPGA
2000
ACM
120views FPGA» more  FPGA 2000»
13 years 8 months ago
A novel high throughput reconfigurable FPGA architecture
With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial...
Amit Singh, Luca Macchiarulo, Arindam Mukherjee, M...