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» High-Level State Machine Specification and Synthesis
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SIGSOFT
2003
ACM
14 years 6 months ago
Behaviour model elaboration using partial labelled transition systems
State machine based formalisms such as labelled transition systems (LTS) are generally assumed to be complete descriptions m behaviour at some level of abstraction: if a labelled ...
Sebastián Uchitel, Jeff Kramer, Jeff Magee
ASE
2005
137views more  ASE 2005»
13 years 5 months ago
Rewriting-Based Techniques for Runtime Verification
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...
Grigore Rosu, Klaus Havelund