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IPPS
1997
IEEE
10 years 7 months ago
A Tool for On-line Visualization and Interactive Steering of Parallel HPC Applications
Tools for parallel systems today range from speciļ¬cation over debugging to performance analysis and more. Typically, they help the programmers of parallel algorithms from the ea...
Sabine Rathmayer
ICCAD
2009
IEEE
117views Hardware» more  ICCAD 2009»
10 years 15 days ago
Binning optimization based on SSTA for transparently-latched circuits
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
Min Gong, Hai Zhou, Jun Tao, Xuan Zeng
BMCBI
2010
218views more  BMCBI 2010»
10 years 2 months ago
Fast multi-core based multimodal registration of 2D cross-sections and 3D datasets
Background: Solving bioinformatics tasks often requires extensive computational power. Recent trends in processor architecture combine multiple cores into a single chip to improve...
Michael Scharfe, Rainer Pielot, Falk Schreiber
CODES
2005
IEEE
10 years 8 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
IEEEPACT
2007
IEEE
10 years 9 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
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