64 search results - page 2 / 13 » High-Performance Extendable Instruction Set Computing |
APCSAC
2006
IEEE
13 years 11 months ago
2006
IEEE
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
SC
1992
ACM
13 years 9 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
IPPS
2010
IEEE
13 years 2 months ago
2010
IEEE
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
ARC
2006
Springer
13 years 8 months ago
2006
Springer
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...