140 search results - page 1 / 28 » High-level design for asynchronous logic |
RSP
2005
IEEE
13 years 10 months ago
2005
IEEE
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
ASYNC
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
ASPDAC
2001
ACM
13 years 8 months ago
2001
ACM
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
IPPS
2007
IEEE
13 years 10 months ago
2007
IEEE
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
SECON
2007
IEEE
13 years 10 months ago
2007
IEEE
—Programming Wireless Sensor Network (WSN) applications is known to be a difficult task. Part of the problem is that the resource limitations of typical WSN nodes force programm...