2 search results - page 1 / 1 » High-level synthesis for large bit-width multipliers on FPGA... |
CODES
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGA...