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ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
11 years 6 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
OSDI
1994
ACM
13 years 5 months ago
HiPEC: High Performance External Virtual Memory Caching
Traditional operating systems use a xed LRU-like page replacement policy and centralized frame pool that cannot properly serve all types of memory access patterns of various appli...
Chao-Hsien Lee, Meng Chang Chen, Ruei-Chuan Chang
ISPASS
2007
IEEE
13 years 10 months ago
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications
This paper proposes a specialized memory structure called CA-RAM (Content Addressable Random Access Memory) to accelerate search operations present in many important real-world ap...
Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad ...
DSD
2009
IEEE
147views Hardware» more  DSD 2009»
13 years 8 months ago
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...
Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu
DATE
2008
IEEE
75views Hardware» more  DATE 2008»
13 years 10 months ago
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization
With technology advances, the number of cores integrated on a chip and their speed of operation is increasing. This, in turn is leading to a significant increase in chip temperat...
Srinivasan Murali, Almir Mutapcic, David Atienza, ...