8 search results - page 2 / 2 » Highly latency tolerant Gaussian elimination |
ICPP
1999
IEEE
13 years 10 months ago
1999
IEEE
The probability of failures in software distributed shared memory (SDSM) increases as the system size grows. This paper introduces a new, efficient message logging technique, call...
ISCAPDCS
2004
13 years 7 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
CJ
2006
13 years 5 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...