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ISCAS
2003
IEEE
78views Hardware» more  ISCAS 2003»
13 years 10 months ago
History-based memory mode prediction for improving memory performance
To increase the bandwidth of synchronous memories that are widely adopted for high performance memory systems, a predictive mode control scheme is proposed to reduce memory latenc...
Seong-Il Park, In-Cheol Park
CF
2007
ACM
13 years 8 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee
ASPLOS
2011
ACM
12 years 8 months ago
MemScale: active low-power modes for main memory
Main memory is responsible for a large and increasing fraction of the energy consumed by servers. Prior work has focused on exploiting DRAM low-power states to conserve energy. Ho...
Qingyuan Deng, David Meisner, Luiz E. Ramos, Thoma...
CLUSTER
2002
IEEE
13 years 9 months ago
Mixed Mode Matrix Multiplication
In modern clustering environments where the memory hierarchy has many layers (distributed memory, shared memory layer, cache,  ¡ ¢  ), an important question is how to fully u...
Meng-Shiou Wu, Srinivas Aluru, Ricky A. Kendall
IPPS
2010
IEEE
13 years 2 months ago
Improving the performance of hypervisor-based fault tolerance
Hypervisor-based fault tolerance (HBFT), a checkpoint-recovery mechanism, is an emerging approach to sustaining mission-critical applications. Based on virtualization technology, H...
Jun Zhu, Wei Dong, Zhefu Jiang, Xiaogang Shi, Zhen...