33 search results - page 2 / 7 » Hybrid CMOS nanoelectronic digital circuits: devices, archit... |
DAC
1996
ACM
13 years 9 months ago
1996
ACM
Aggressive voltage scaling to 1V and below through technology, circuit, and architecture optimization has been proven to be the key to ultra low-power design. The key technology t...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
CAMP
2005
IEEE
13 years 11 months ago
2005
IEEE
Abstract— The promise of next-generation computer technologies, such as nano-electronics, implies a number of serious alterations to the design flow of digital circuits. One of ...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS pro...