43 search results - page 1 / 9 » Hybrid Cache Architecture for High Speed Packet Processing |
HOTI
2005
IEEE
13 years 10 months ago
2005
IEEE
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
HPCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
VTC
2007
IEEE
13 years 10 months ago
2007
IEEE
Abstract-In this paper, a Q-learning-based hybrid automatic repeat request (Q-HARQ) scheme is proposed to achieve efficient resource utilization for high speed downlink packet acc...
RTAS
1997
IEEE
13 years 8 months ago
1997
IEEE
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
ECOOP
1998
Springer
13 years 8 months ago
1998
Springer
In this paper, we propose architectural support for object manipulation, stack processing and method invocation to enhance the execution speed of Java bytecodes. First, a virtual a...