121 search results - page 1 / 25 » Hybrid cache architecture with disparate memory technologies |
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
IPPS
1992
IEEE
13 years 8 months ago
1992
IEEE
This paper presents a hybrid shared memory architecture which combines the scalability of a multistage interconnection network with the contention reduction benefits of coherent c...
OTM
2004
Springer
13 years 10 months ago
2004
Springer
Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are diffi...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...