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» IC Analyses Including Extracted Inductance Models
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DAC
1999
ACM
13 years 8 months ago
IC Analyses Including Extracted Inductance Models
IC inductance extraction generally produces either port inductances based on simplified current path assumptions or a complete partial inductance matrix. Combining either of thes...
Michael W. Beattie, Lawrence T. Pileggi
ISCAS
2006
IEEE
101views Hardware» more  ISCAS 2006»
13 years 10 months ago
Neuromimetic ICs and system for parameters extraction in biological neuron models
—This paper presents an analog neuromimetic integrated circuit and an associated system dedicated for experiments of parameters extraction in biological neuron models. The IC bas...
Sylvain Saïghi, Yannick Bornat, Jean Tomas, S...
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
13 years 9 months ago
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses
Due to the increasing operating frequencies and the manner in which the corresponding integrated circuits and systems must be designed, the extraction, modeling and simulation of ...
Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie...
DATE
1999
IEEE
92views Hardware» more  DATE 1999»
13 years 8 months ago
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics
Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computation...
Peter Feldmann, Sharad Kapur, David E. Long
3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
13 years 11 months ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...