128 search results - page 2 / 26 » ILP-based optimization of sequential circuits for low power |
DATE
2007
IEEE
14 years 3 days ago
2007
IEEE
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as hig...
VTS
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...
ISLPED
2000
ACM
13 years 9 months ago
2000
ACM
This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...
ASPDAC
2000
ACM
13 years 10 months ago
2000
ACM
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...