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ISVLSI
2007
IEEE
116views VLSI» more  ISVLSI 2007»
13 years 10 months ago
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures
As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alter...
Soumya Eachempati, Narayanan Vijaykrishnan, Arthur...
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
13 years 11 months ago
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
SLIP
2009
ACM
13 years 11 months ago
Closed-form solution for timing analysis of process variations on SWCNT interconnect
In this paper, a comprehensive and fast method is presented for the timing analysis of process variations on single-walled carbon nanotube (SWCNT) bundles. Unlike previous works t...
Peng Sun, Rong Luo
DATE
2010
IEEE
159views Hardware» more  DATE 2010»
13 years 9 months ago
A rapid prototyping system for error-resilient multi-processor systems-on-chip
—Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only...
Matthias May, Norbert Wehn, Abdelmajid Bouajila, J...