30 search results - page 1 / 6 » Impact of Sharing-Based Thread Placement on Multithreaded Ar... |
ISCA
1994
IEEE
13 years 8 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
IPPS
2007
IEEE
13 years 10 months ago
2007
IEEE
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
PDP
2011
IEEE
12 years 8 months ago
2011
IEEE
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
ISCA
1996
IEEE
13 years 8 months ago
1996
IEEE
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
SASP
2008
IEEE
13 years 10 months ago
2008
IEEE
Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, ...