Sciweavers

43 search results - page 2 / 9
» Implementing Performance Competitive Logical Recovery
Sort
View
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
13 years 11 months ago
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmo...
FROCOS
2000
Springer
13 years 8 months ago
Compiling Multi-Paradigm Declarative Programs into Prolog
This paper describes a high-level implementation of the concurrent constraint functional logic language Curry. The implementation, directed by the lazy pattern matching strategy of...
Sergio Antoy, Michael Hanus
ENTCS
2010
139views more  ENTCS 2010»
13 years 4 months ago
Spartacus: A Tableau Prover for Hybrid Logic
Spartacus is a tableau prover for hybrid multimodal logic with global modalities and reflexive and transitive relations. Spartacus is the first system to use pattern-based blocking...
Daniel Götzmann, Mark Kaminski, Gert Smolka
EDCC
2006
Springer
13 years 8 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
VLDB
1997
ACM
109views Database» more  VLDB 1997»
13 years 9 months ago
Logical and Physical Versioning in Main Memory Databases
We present a design for multi-version concurrency control and recovery in a main memory database, and describe logical and physical versioning schemes that allow read-only transac...
Rajeev Rastogi, S. Seshadri, Philip Bohannon, Denn...