62 search results - page 1 / 13 » Implementing the High Level Architecture in the Virtual Test... |
WSC
2004
13 years 5 months ago
2004
The Virtual Test Bed (VTB) is a prototype of a virtual engineering environment to study operations of current and future space vehicles, spaceports, and ranges. The HighLevel Arch...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
MTV
2005
IEEE
13 years 10 months ago
2005
IEEE
Our mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architec...
CORR
2004
Springer
2004
Springer
Using Wireless Sensor Networks to Narrow the Gap between Low-Level Information and Context-Awareness
13 years 4 months ago
Wireless sensor networks are finally becoming a reality. In this paper, we present a scalable architecture for using wireless sensor networks in combination with wireless Ethernet...
ATAL
2007
Springer
13 years 10 months ago
2007
Springer
In this paper we describe a multi-agent simulation called the Human Agent Virtual Environment (or HAVE). HAVE is a test bed to explore agent-environment interaction in multiagent ...