29 search results - page 3 / 6 » Improved Fault Emulation for Synchronous Sequential Circuits |
ICCAD
2000
IEEE
13 years 10 months ago
2000
IEEE
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
ICCAD
2000
IEEE
13 years 10 months ago
2000
IEEE
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors ap...
DATE
1997
IEEE
13 years 10 months ago
1997
IEEE
The paper proposes a novel approach in an attempt to solve the test problem for sequential circuits. Up until now, most of the classical test pattern techniques use a number of al...
ATS
2000
IEEE
13 years 10 months ago
2000
IEEE
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...