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» Improved Memory-Access Analysis for x86 Executables
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EUROPAR
1997
Springer
13 years 9 months ago
Modulo Scheduling with Cache Reuse Information
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
Chen Ding, Steve Carr, Philip H. Sweany
IPPS
2009
IEEE
13 years 12 months ago
Implementing and evaluating multithreaded triad census algorithms on the Cray XMT
Commonly represented as directed graphs, social networks depict relationships and behaviors among social entities such as people, groups, and organizations. Social network analysi...
George Chin Jr., Andrès Márquez, Sut...
ASPLOS
2004
ACM
13 years 10 months ago
Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign
Tracing garbage collectors traverse references from live program variables, transitively tracing out the closure of live objects. Memory accesses incurred during tracing are essen...
Chen-Yong Cher, Antony L. Hosking, T. N. Vijaykuma...
EUROPAR
2001
Springer
13 years 9 months ago
Performance of High-Accuracy PDE Solvers on a Self-Optimizing NUMA Architecture
High-accuracy PDE solvers use multi-dimensional fast Fourier transforms. The FFTs exhibits a static and structured memory access pattern which results in a large amount of communic...
Sverker Holmgren, Dan Wallin
ISCA
1991
IEEE
162views Hardware» more  ISCA 1991»
13 years 8 months ago
Comparison of Hardware and Software Cache Coherence Schemes
We use mean value analysis models to compare representative hardware and software cache coherence schemes for a large-scale shared-memory system. Our goal is to identify the workl...
Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary...